Wafer-level Inspection

As today’s semiconductor designs continually become smaller and denser, the challenges of wafer inspection are constantly escalating. Extremely small feature sizes can require 50X or higher objective lens magnification and highly programmable top-lighting/back-lighting, along with ultra high-resolution accuracy and repeatability.

While inline wafer inspection can require the investment in very expensive, dedicated specialized systems, highly-adaptable feature-rich metrology platforms such as VIEW’s Summit and Pinnacle can provide economically advantageous alternatives for lab-oriented and near-line inspection/qualification of wafer level processes.